1) Field of the Invention
The present invention relates to an information processing unit, which executes store instruction for storing data in predetermined store area on the main memory or cache memory and a store instruction control method.
2) Description of the Related Art
Conventionally, there resides an information processing unit, which executes store instruction for storing data in a predetermined store area (for example, refer to patent document 1 below).
FIG. 7 is a block diagram showing the configuration of a conventional information processing unit 100. As shown in FIG. 7, the conventional information processing unit 100 comprises an instruction processing section 10, a arithmetic unit 20, an address register 21, a arithmetic register 22, store ports 30-0-30-n (n is an integral number equal to or larger than 0; here, an integral number equal to or larger than 2), an align section 40, store data buffers 50-0-50-n (n is an integral number equal to or larger than 0; here, an integral number equal to or larger than 2), a cache memory (storage area) 60 and a reset section 81.
Here, each of the above constituent elements of the conventional information processing unit 100 shown in FIG. 7 will be described based on the operation thereof. FIG. 8 is a time chart for illustrating the steps (operation of the information processing unit 100) of the store instruction control method by the conventional information processing unit 100 shown in FIG. 7. In FIG. 8, T1-T12 indicate a time unit respectively; that is, a control clock unit respectively in the information processing unit 100.
As shown in FIGS. 7 and 8, in the information processing unit 100, first of all, the instruction processing section 10 decodes an instruction held by instruction cache (not shown) (refer to T1 in FIG. 8). Here, when the instruction decoded by the instruction processing section 10 is a store instruction (store request), the instruction processing section 10 obtains the length of the data to be stored (hereinafter, referred to as store data length; indicated as LENGTH in the figure), align instruction information, which indicates right/left alignment of the store data (indicated as ALIGN in the figure), a number (value) or immediate operand of the address register 21, which is used for computing the address (hereinafter, referred to as store address) of the store destination by the arithmetic unit 20 and a number (value) of the arithmetic register 22, which holds the data (hereinafter, referred to as store data) to be stored in accordance with the store instruction along with the decoded store instruction.
When the address register 21 used for computing of the store address by the arithmetic unit 20 is determined (refer to T2 in FIG. 8), the instruction processing section 10 issues the decoded store instruction, the store data length and the align instruction information to any one of the store ports 30-0-30-n (here, store port 30-0) (refer to T3 in FIG. 8).
On the other hand, when the address register 21 used for computing the store address is determined (refer to T2 in FIG. 8), the arithmetic unit 20 carries out the computation of the store address using the address register 21 (refer to T3 in FIG. 8). The store address obtained as the computation result of the arithmetic unit 20 is temporarily held in a storing register (here, since the address register 21 is a general purpose register, in the address register 21).
Then, the store address calculated by the arithmetic unit 20 is issued to the store ports 30-0-30-n (refer to T4 in FIG. 8). Here, the store address is supplied to a pipeline of a memory processing device, which includes at least store ports 30-0-30-n. By being flowed through the pipeline, the store address is converted to an address (physical address; hereinafter, when the address is not discriminated from the store address held by the address register 21, referred to as just store address) on the storage area (here, cache memory 60), which is the actual store destination, using a Translation Lookaside Buffer (TLB; not shown). And the converted store address is issued to the store port 30-0 (refer to T4 in FIG. 8). When the issuance of the store address from the address register 21 is completed, the address register 21 is released and is available for the next processing.
The store port 30-0 is adapted so as to hold information, which indicates that the store instruction, store address (physical address), and store data length have been received (here, flags; refer to “VALID”, “ADRS”, and “LENGTH” in FIG. 7). When the store instruction is received, a VALID flag 30a is set to ON; when the store address is received, an ADRS (Address) flag 30b is set to ON; and when the store data length is received, a LENGTH flag 30c is set to ON (refer to T5 in FIG. 8).
After checking that the store instruction has been issued to the store port 30-0, the instruction processing section 10 unlocks the issuance of the store data from the arithmetic register 22 to issue the store data, which are to be stored in response to the store instruction held by the arithmetic register 22, to the store data buffers 50-0-50-n (here, store data buffer 50-0) (refer to T6 in FIG. 8). That is, in the conventional information processing unit 100, it is arranged so that, even when the number (value) of the arithmetic register 22 has been determined, the issuance of the store data from the arithmetic register 22 are restrained (interlocked) until the issuance of the store instruction to the store port 30-0 is completed.
Then, the store data held by the arithmetic register 22 are issued to the store data buffer 50-0 corresponding to the store port 30-0 (refer to T7 in FIG. 8). Here, first of all, the align section 40 aligns the store data issued from the arithmetic register 22 using the store data length and align instruction information (hereinafter, they will be referred to as align information) issued to the store port 30-0 along with the store instruction (refer to T8 in FIG. 8). After that, the store data aligned by the align section 40 are held by the store data buffer 50-0 (refer to T9 in FIG. 8). When the issuance of the store data from the arithmetic register 22 has been completed, the arithmetic register 22 is released and is available for the next processing.
Further, the store port 30-0 is adapted so as to hold information (here, a flag; refer to “RSTDV” in FIG. 7), which indicates whether or not the store data has been held in the store data buffer 50-0. When the store data buffer 50-0 holds the store data issued from the arithmetic register 22, the RSTDV (Received Store Data Valid) flag 30d is set to ON (refer to T9 in FIG. 8).
When the store port 30-0 holds the store address (refer to T5 in FIG. 8), the instruction processing section 10 takes out page attribute of the storing area and determines the exception (refer to T6 in FIG. 8). That is, the instruction processing section 10 determines whether or not the store address as the storing area can be written (stored) When the store address can be stored, the instruction processing section 10 notifies the “non-exception” to the store port 30-0. On the other hand, when the store address cannot be stored, the instruction processing section 10 notifies the exception to the store port 30-0, and cancels the execution of the store instruction.
The store port 30-0 is adapted so as to hold information (here, a flag; refer to “PSTV” in FIG. 7) indicating the result (Y/N) of the exception determination. When the determination result of the exception received from the instruction processing section 10 is “non-exception”, a PSTV (Post Status Valid) flag 30e is set to ON. On the other hand, when the determination result is “exception”, the PSTV flag 30e is set to OFF.
When the store instruction, the store address and the length of the store data have been held in the store port 30-0, the result of the exception determination of the store instruction is “non-exception” and the store data have been held in the store data buffer 50-0 (i.e., each of the VALID flag 30a, the ADRS flag 30b, the LENGTH flag 30c, the PSTV flag 30e and the RSTDV flag 30d is ON), and every instruction prior to the store instruction has been completed, the instruction processing section 10 determines that the store instruction can be carried out, and notifies the store permission to the store port 30-0 (refer to T10 in FIG. 8).
The store port 30-0 is adapted so as to hold the information indicating whether or not the store permission is received from the instruction processing section 10 (here, a flag; refer to “READY” in FIG. 7). When the store permission is received from the instruction processing section 10, the READY flag 30f is set to ON.
When the READY flag 30f of the store port 30-0 is set to ON, the store instruction is carried out (refer to T11 in FIG. 8), store data held in the store data buffer 50-0 are written on a predetermined address in the cache memory 60 based on the store address held in the store port 30-0; and thus, the processing of the store instruction is completed (refer to T12 in FIG. 8).
As described above, the conventional information processing unit 100 is arranged so that the store instruction is issued first from the instruction processing section 10 to the store ports 30-0-30-n; and then the store data, which is the operation result by the arithmetic unit 20, is issued from the arithmetic register 22 to the store data buffers 50-0-50-n. That is, the processing is carried out in-order.
Accordingly, as shown in FIG. 7, the conventional information processing unit 100 is provided with the reset section 81, which can reset the RSTDV flag 30d in the store ports 30-0-30-n to OFF, and is arranged so that when the store instruction, which is issued from the instruction processing section 10, is held by the store ports 30-0-30-n, the reset section 81 resets the RSTDV flag 30d to OFF (refer to T5 in FIG. 8).
That is, in the conventional information processing unit 100, since the processing is carried out in-order, there is no such case where, at a point of time when the store instruction is held by the store ports 30-0-30-n, store data are held in the corresponding store data buffers 50-0-50-n. Therefore, it is arranged so that, at a point of time when the store instruction is held by the store ports 30-0-30-n, the reset section 81 resets the RSTDV flag 30d to OFF. Owing to this arrangement, the following errors are prevented. That is, for example, store data, which are different from the proper store data to be stored, are held in the corresponding store data buffers 50-0-50-n, and the data, which are not to be stored, are stored erroneously; or when the store data buffers 50-0-50-n do not hold the store data, since the RSTDV flag 30d is erroneously set to ON, the store instruction is not carried out, etc.
[Patent document 1] Japanese Patent Laid-Open (Kokai) HEI 5-289848
In the above-described conventional information processing unit 100, after the instruction processing section 10 decodes the instruction and before issuing the store instruction to the store ports 30-0-30-n, the number (value) of the address register 21, which is used for computing the store address by the arithmetic unit 20, has to be determined. Also, before issuing the store data to the store data buffers 50-0-50-n, the number (value) of the arithmetic register 22, which holds the store data, has to be determined. The order that the numbers of the address register 21 and the arithmetic register 22 are determined is not fixed.
However, in the conventional information processing unit 100, as described above, the processing is carried out in-order such that the store instruction is issued first from the instruction processing section 10 to the store ports 30-0-30-n, and then, the store data are issued from the arithmetic register 22 to the store data buffers 50-0-50-n. Therefore, even when the number of the arithmetic register 22 is determined and the store data are held in the arithmetic register 22 before the number of the address register 21 is determined, the issuance of the store data from the arithmetic register 22 to the store data buffers 50-0-50-n is locked until the number of the address register 21 is determined and the issuance of the store instruction is checked; and thus, has to wait for the issuance of the store data.
Therefore, while the issuance of the store data from the arithmetic register 22 to the store data buffers 50-0-50-n is waited for, needless to say, the release of the arithmetic register 22, which holds the store data, also has to be waited for. During that period, the arithmetic register 22 cannot be used for another computing, thus, the operation efficiency of the arithmetic register 22 is not satisfactory.